Flashing a DE0 nano bitstream on macOS using UrJTAG

Posted on July 8, 2018


After creating a Docker image on macOS with Altera’s Intel’s Quartus Prime, I needed a way to load the bitstream from Quartus onto my FPGA. As Docker on mac doesn’t support USB passthrough, I needed a solution that ran natively on macOS, which ruled out basically everything except open source software. I managed to compile a tool called UrJTAG on my mac, and added support for the DE-0 Nano’s FPGA to it by following this guide.


Building UrJTAG

  1. We need to build the UrJTAG tool, so execute the following in the terminal
brew install libftdi libusb pkg-config
git clone https://github.com/C-Elegans/urjtag.git
cd urjtag
./configure --with-libftdi --with-libusb --withftd2xx --with-inpout32 --enable-python=no
make -j4
make install     # Use sudo if this gives an error
  1. Next, to test UrJTAG, plug the DE-0 Nano plugged into the computer, run jtag, and type the following lines into the prompt:
cable usbblaster

The program should print out the following:

IR length: 10
Chain length: 1
Device Id: 00000010000011110011000011011101 (0x020F30DD)
  Manufacturer: Altera (0x0DD)
  Part(0):      EP4CE22 (0x20F3)
  Stepping:     0
  Filename:     /usr/local/share/urjtag/altera/ep4ce22/ep4ce22
warning: USB-Blaster frequency is fixed to 12000000 Hz
warning: unimplemented mode 'ABSENT' for TRST

if instead, it prints out:

IR length: 10
Chain length: 1
Device Id: 00000010000011110011000011011101 (0x020F30DD)
  Manufacturer: Altera (0x0DD)
  Unknown part! (0010000011110011) (/usr/local/share/urjtag/altera/PARTS)

then something went wrong in your UrJTAG installation. To fix, type quit into the prompt, then run

mkdir -p /usr/local/share/urjtag/altera/ep4ce22
cp data/altera/ep4ce22 /usr/local/share/urjtag/altera/ep4ce22

and try step 2 again.

  1. Now that UrJTAG is working, we need to generate the programming files for the FPGA. Because UrJTAG cannot understand the .sof file format Quartus uses, we need to convert the file into a .svf file

    1. Open an existing FPGA design inside Quartus, and compile it
    2. Open the programmer, and load the device programming file into it (it should already be there)

    1. Click File->Create JAM, JBC, SVF, or ISC File…

    1. Change File Format: to Serial Vector Format (.svf) and click OK

Flashing the FPGA

Navigate to the location where the .svf file was generated, run jtag and type the following into the prompt:

cable usbblaster
part 0
svf yourfile.svf

and the FPGA should be flashed! To make uploading easier, you can put the above commands in a file, and run

jtag cmdfile

instead of typing the commands in each time.